1. Field of the Invention
The invention relates to a semiconductor memory device and, more particularly, to a readout circuit for a semiconductor memory device arranged of a virtual ground line type memory cell array.
2. Description of the Related Art
As the function of mobile telephones is improved or the application of memory cards and files is increased, flash memories have been scaled up in the memory size. For the purpose, particularly cost down, a variety of devices have been developed where the effective cell area is minimized, using a multilevel storage technique for storing multilevel data, not less than three levels, in each memory cell or a memory cell array technique of virtual ground line type where the drain and source of each transistor are arranged common to any two adjacent memory cells along a row.
Particularly, such a virtual ground line type memory cell array technique allows the cell area to be decreased by the scheme of circuitry arrangements and hence has an advantage of producing a smaller chip-area device with the use of a known process. However, as its virtual ground line construction permits leak currents from the adjacent memory cell during the readout action to be hardly negligible, the memory cell array has to be modified for increasing the speed of the readout action.
One of the conventional virtual ground line type memory cell array techniques is disclosed in JP-A 3-176895 (1991) where the drawback of leak current is overcome.
FIG. 9 illustrates a virtual ground line type memory cell array of EPROM according to the technique disclosed in JP-A 3-176895 (1991). Each memory cell MC in the memory cell array is a known electrically programmable insulating gate n-channel field effect transistor. The memory cell MC is connected at the control gate to a row line WL, at the source to a source column line SL, and at the drain to a drain column line DL. Both the source column line SL and the drain column line DL are buried bit lines in the diffusion area.
For selecting and reading a memory cell MCb, for example, its corresponding row line WLa is selectively activated by shifting to a positive high potential and, simultaneously, the source column line SLb is grounded via a MOSFET 34. The other lines at the right of the memory cell MCb including the drain column line DLb remain at the floating state. Also, its corresponding drain column line DLa is applied with a readout drain bias potential DRB from a node 33 via another MOSFET 32. The adjacent source column line SLa is applied with a drain bias voltage RDP from a node 31 via a transistor 30. The other source lines at the left of the source column line SLa all remain at the floating state.
The readout drain bias potential RDP applied to the node 31 is equal to the potential DRB applied to the node 33, for example, 1.2 V As the two potentials are equal, the readout current is fully received by the memory cell MCb to be read, but not transferred to the adjacent memory cell MCa. Accordingly, leakage of the current to any adjacent memory cell can be prevented while the high-speed access is achieved.
Alternatively, another conventional virtual ground line type memory cell array is disclosed in JP-A 2003-323796 where the precharge level on the bit lines can be controlled.
FIG. 10 illustrates a circuitry arrangement where a current mirror circuit, disclosed in JP-A 2003-323796, for generating a precharge is used in a virtual ground line type memory cell array of a floating gate structure of, e.g., a flash memory. The current mirror circuit shown in FIG. 10 feeds a bit line L3 with a precharge via a signal line DATAP. The current mirror circuit causes the potential on the signal line DATAP (for a data P signal) to be equal to the potential at the signal line DATA (for a data signal). Accordingly, as the two signal lines DATA and DATAP are controlled to remain equal in the potential, the flow of charge current from the bit line L2 to the bit line L3 is inhibited. Since the precharging period is shortened and the readout current for reading a memory cell A is prevented from discharging to the bit line L3, the high-speed access can be achieved.
Using the foregoing conventional technique, the readout action is carried out where the drain current applied to the drain of a memory cell to be read is declined by the resistance of the bit lines and the effect of a memory cell current through the bit lines. As other memory cells adjacent to the memory cell to be read has its leak current much smaller than the memory cell current on the memory cell to be read, their drain potential (appropriately referred to as “counter potential” hereinafter) will be declined to a minimum. Accordingly, there will be occurred a difference of the potential between the drain of the memory cell to be read and the drain of each adjacent memory cell in the memory cell array regardless of controlling the potential on the selected bit line to a level equal to the potential on the unselected bit line, hence permitting the generation of leak current. The flow of leak current will thus decline the memory cell current through the selected bit line. As the memory cell current is declined, its measurement by a sense amplifier will drop down hence lowering the marginal factor in the readout action.
More particularly, when the adjacent memory cell MCa shown in FIG. 9 is not high in the threshold voltage, the potential of the memory cell MCb to be read is attenuated at the drain by the readout current and will thus produce a difference between the drain and the source of the adjacent memory cell MCa. As a result, the drain potential RDB on the adjacent memory cell will generate a leak current.